• Shane McKeown - Principal Hardware Engineer, Calnex Solutions

The new draft revision of G.8273.2 is proposing much tighter requirements for network equipment transferring time compared to the current published revision i.e. Max |TE| of Class A & Class B are 100nsec & 70nsec respectfully, the proposed values for Class C & Class D are 20nsec & 10nsec. Achieving a near order of magnitude improvement in accuracy will not come from ‘tweaking’ the current design, it is like to require a major overhaul of key aspects of the design.

The challenges for test equipment designers is to deliver test solutions achieving sub-nsec accuracy to enable the Network Equipment designers to prove their designs meet Class C & D performance. To achieve this, a fresh approach to key aspects of the test system architecture is required to achieve this goal.

While development test equipment is quite different from development network equipment, a number of core principles apply to any design team embarking of designing equipment compliant to the new high accuracy standard. This poster will set out the engineering challenge, provide insight to key aspects of design innovation to produce a step function in performance and, most importantly, discuss how we went about verifying the actual performance achieved the theoretical expectation.